1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a fuse circuit.
2. Related Background Art
A semiconductor memory such as a DRAM has a redundant circuit for replacing a defective memory with a redundant memory. The circuit has a program circuit for storing an address of the redundant memory. If any defective cell exists, the address of the defective cell is programmed in the LSI, so that the redundant cell is accessed at the time of access with the address during the LSI operation. The redundant circuit has a program element (fuse) formed of polysilicon or aluminum wiring. The replacement address programming is conducted by blowing the fuse using a laser device.
There has been suggested a fuse circuit having an arrangement wherein circuit blocks for determining a replacement address are disposed on one side of a fuse area and return wires are used, for example, in Japanese Laid-Open Patent Publication (Kokai) No. 2003-142582.
Referring to FIG. 7, there is shown a pattern diagram of a fuse circuit described in the patent publication.
Circuit blocks 101 are disposed on one side of a fuse region. A plurality of fuses 106 are arranged symmetrically about a common wire 107. Fuses 106b, 106d, and 106f arranged relatively distant from the circuit blocks 101 are connected to the corresponding circuit blocks, respectively, via return wires 103.
Referring to FIG. 8, there is shown a layout plan view of the fuse circuit shown in FIG. 7.
A plurality of fuse wires 201 are arranged perpendicularly to a common wire 203. A return wire 202 is connected at one end of each of the fuse wires 201, with the fuse wires 201 and the corresponding return wires 202 arranged alternately.
Referring to FIG. 9, there is shown a cross-sectional view taken on line D-D of the fuse circuit shown in FIG. 8. The fuse wires 201 are formed by upper-layer wiring and the return wires 202 are formed by lower-layer wiring.
The fuse wires 201 are arranged so as to satisfy the positional relation of preventing a short circuit between the return wires and the fuse wires caused by scattering of material 300 of the fuse wires due to irradiation with a laser beam as shown in FIG. 10. In other words, the fuse wires 201 are arranged at a pitch A so as not to be damaged by a laser beam at the time of fuse cutting as shown in FIG. 8.
In addition, Japanese Laid-Open Patent Publication (Kokai) No. 2002-368094 discloses a technology of an arrangement of return wires just under a fuse element.
In a semiconductor memory device, there are various fuses on the current chip and the number of fuses thereon is increasing. Therefore, the ratio of the fuse area to the chip area is increasing. The layout, however, as shown in Japanese Laid-Open Patent Publication (Kokai) No. 2003-142582 has problems of a wide fuse pitch and a large fuse area.
Furthermore, in Japanese Laid-Open Patent Publication (Kokai) No. 2002-368094, it is necessary to cut a fuse layer surely in actual laser trimming. Therefore, wiring just under the fuse layer is irradiated with a laser beam immediately after the cutting, and thus there is an extremely high risk. Moreover, a fuse wire has such a problem that it spatters breaking a part of the surrounding insulating layer in the instant of being blown at a high temperature, thus adversely affecting return wires just under and close to it.